Pseudo-random sequence built from shift resisters and exclusive-OR gates often are used to supply binary test data. If constructed from 100-kΩ ECL parts, such generators can run at up to 200 Mbits/s.Although an N-bit shift register can be connected to generate a sequence that repeats every 2^N-1 bits,if it should start up in its all-zeros state, no output will be generated. What is needed is a counter to inject a 1 or to preload the shift register whenever N consecutive zeros are detected. The illustratesd circuit generates a 127-bit sequence. It provides a synchronization pulse once per repetition without using additional parts ,and it is guaranted to start. It uses the “wired-OR” property of ECL to generate a 1-bit period negative sync pulse when six zero are present (only five of these zeros are consecutive; a different set of N-1 bits might br needed if a longer shift register is used ). The sync pulse parallel-loads the shift register with the next state in the sequence. As a result, no seven-zero detector is needed to start the generator.